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FPGASynth: PhaseDistortionOscillator

Introduction

The basic theory behind a Phase Distortion Synthesis is described at http://en.wikipedia.org/wiki/Phase_distortion_synthesis. It involves running the ordinary linear sinusoidal phase through a distortion function to produce near-arbitrary waveforms.

Octave Model

GNU Octave (available from http://www.gnu.org/software/octave/download.html) is an open-source mathemtical modeling language that's compatible with the commercial Matlab package.

Download the model here: Attach:pdo_octave_model.zip

The Octave model for the PDO consists of the following files:

Running octave_test_pdo from the Octave command line should produce 2 output plots. The first, labelled "Phase Map", shows the phase distortion function graphically. The second plot shows 2 periods of the resulting waveform.

In addition to the raw PDO model, two test "tunes" are provided which demonstrate usage of the model: pdo_tune and pdo_better_tune. The first just uses the PDO to play a simple little song, and consists of the files:

The second is more sophisticated (and may take a VERY long time to run! you have been warned):

All three of the octave_test_* programs output a .raw file. This file can be opened in your audio editor of choice, the format is 48000 Hz Signed 16-bit Mono PCM.

VHDL Model (for Altera FPGAs)

Download VHDL Model v2 here: Attach:pdo_vhdl_v2.zip

The VHDL model here targets the Altera CycloneII EP2C35F672C6 device (as found on Altera DE2 boards).

File manifest:

Project files for the freely downloadable Quartus II Web Edition v6.0 Build 202. This software can be used to run software simulations of the oscillator, sample waveform stimulus files are provided in the package.

Altera altsyncram mega function instantiation of a single port 12000 word by 16 bit ROM. If porting to another architecture, this needs to be replaced with a ROM model that has 1 cycle of read latency!

Arbiter for the quarter-wave ROM above, allowing it to be shared among multiple oscillator instances. Example presented here is a 4-port arbiter, but it's very easy to make it as large as necessary. Up to 11 has been tested, and still synthesized to over 100 Mhz on the Cyclone II.

Quarter-wave symmetry mapping function. Creates a virtual 48000 word single-cycle Sin LUT from the 12000 word quarter-wave ROM.

Altera lpm_mult mega function instantiation of an 18x18 bit signed multiplier. A sample 4-port arbiter for the multiplier is provided.

Flexible, reusable linear phase generator block with synchronous load.

The phase distorter implements the FSM to compute the distortion function. PDO is the oscillator top-level.

Sinusoidal oscillator that shares a common sin LUT arbiter interface. Purely combinational, no multipliers are required by this block.

Example top-level with 4 PDO instances. This top-level models 4 phase distortion oscillators (with built-in output gain) using only 1 signed 18x18 multiplier.

Instance 1 and 2 output a "Sin Square" shape at 100hz and 200hz respectivelly, while instances 3 and 4 will output a "Sin Pulse" (see "Waveform Presets" below) wave at 400hz and 800hz.

A sample instantiation of the sinusoidal oscillator is provided, but the SIN arbiter will need to be extended with more ports if you want to actually hook it up.

In theory, 140 PDO instances (with output gain) could fit into a CycloneII EP2C35F672C6 device; however scaling issues with the Sin LUT would likely be encountered. Possible solutions are 1) use a dual-port ROM, 2) use 2 full-sized ROMs (the FPGA has enough memory bits for it), or 3) half the size of the ROM (use linear interpolation in full_sin_lut.vhd to re-consutrct) and use 4 of the resulting ROMs. If #1 and #3 are combined you should be able to get 8 effective Sin ROMs.

VHDL Model Interfaces

Clock and control:

PDO parameters:

Phase generator control:

Sin LUT arbiter signals:

Multiplier arbiter signals:

Audio output bus:

Waveform Presets

Here are some interesting waveform presets. The first 9 values are the kneepoint constants, and the last value is the sin lut enable bit.

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Page last modified on December 27, 2006, at 04:33 AM